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Verilog HDL User-Defined Primitive Declaration error at <location>: incorrect number of inputs for UDP table entry <text>

CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in Verilog Design File (.v), you entered an incorrect number of inputs for the specified UDP table entry. The number of inputs in the UDP table entry must match the number of input ports in the primitive.
ACTION: Edit either the UDP table entry or the UDP input port list so that the number of input fields in the UDP table matches the number of input ports in the primitive.

See also:

Section 8.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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