Quartus

Verilog HDL syntax error at <location>: table entry is missing colon ':' I/O separator

CAUSE: In a User-Defined Primitive (UDP) Definition at the specified location in a Verilog Design File (.v), one of the lines of the UDP table definition is missing the colon character (:) that separates inputs from outputs.
ACTION: Insert a colon (:) between the inputs and outputs in the table.

See also:

Section 8 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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