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Verilog HDL User-Defined Primitive Declaration error at <location>: incorrect output field length in UDP table <name>

CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in Verilog Design File (.v), you entered an incorrect output field length in a UDP table. A UDP table can have only a single 1-bit output signal.
ACTION: Correct the table output so it has only a single 1-bit output signal.

See also:

Section 8.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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