Quartus

Verilog HDL error at <location>: Task Enable Statement must not be used outside of sequential constructs

CAUSE: In a Verilog Design File (.v) at the specified location, you used a Task Enable Statement in a concurrent construct. However, tasks can be called only from sequential constructs.
ACTION: Move the Task Enable Statement to a sequential construct.

See also:

Section 10.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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