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Verilog HDL error at <location>: task <name> is not declared

CAUSE: In a Verilog Design File (.v) at the specified location, you used a task name that has not been declared. This message may occur if the task name does not match the name in the Task Declaration, or because the task was not declared correctly in a Task Declaration.
ACTION: Make sure the task name matches the task name in the Task Declaration, or declare the task in a Task Declaration.

See also:

Section 10 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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