| CAUSE: | In a Task Definition at the specified location in a Verilog Design File (.v), you defined a task that is not being enabled or run correctly. For example, the task may have been called as a function; however, functions have a return value, while tasks do not. |
| ACTION: | Make sure the Task Enable Statement has the correct syntax, with no return value, or change the Task Definition. |
See also:
Section 12.1 and 12.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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