Quartus

Verilog HDL Module Instantiation error at <location>: too many ports used in Module Instantiation

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you used more ports than the number of ports specified in the Module Definition.
ACTION: Make sure the Module Instantiation uses no more ports than the number of ports specified in the Module Defintion.

See also:

Section 12.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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