Quartus

Verilog HDL Module Definition error at <location>: too many parameters for module instance

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you specified parameters for a module, but the number of parameters specified in the Module Instantiation is more than the number of parameters specified in the Module Definition.
ACTION: Make sure the number of parameters in the Module Instantiation does not exceed the number of parameters in the Module Definition.

See also:

Section 12.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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