Quartus

Verilog HDL User-Defined Primitive Declaration error at <location>: missing present state field in UDP table <text>

CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you used a UDP sequential table, but the UDP table is missing the present state field, which is required.
ACTION: Edit the design to include a present state field in the UDP table, in the following format:
[inputs : present state : next state]

See also:

Section 8 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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