Quartus

Verilog HDL Gate Instantiation error at <location>: unconnected terminal in instantiation of gate <name>

CAUSE: In a Gate Instantiation at the specified location in a Verilog Design File (.v), you instantiated the specified gate but left one of the terminals unconnected. This error could also be caused by accidentally using two commas instead of one.
ACTION: Connect all the terminals in the Gate Instantiation, and remove any accidental duplicate commas.

See also:

Section 7 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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