| CAUSE: | In a Verilog Design File (.v) at the specified location, you used the specified variable, but the variable is not declared. This error can also occur if you reference a hierarchical name. Hierarchical names are not supported in Quartus II Verilog HDL, except in Defparam Statements. For more information on which Verilog HDL hierarchical structures are supported in the Quartus II software, refer to Hierarchical Structures (Quartus II Verilog HDL Support). |
| ACTION: | Declare the variable, or make sure that you are not referencing a hierarchical name. |
See also:
Section 6.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
Quartus II Support for Verilog 2001
Quartus II Verilog HDL Support
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