Quartus

Verilog HDL Compiler Directive error at <location>: predefined text macro <name> cannot be undefined

CAUSE: In a Verilog Design File (.v) at the specified location, you used an `undef Compiler Directive for the specified macro name; however, the specified macro is a predefined macro and cannot be undefined.
ACTION: Remove the `undef directive.

See also:

Section 19.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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