Quartus

Verilog HDL Module Declaration error at <location>: top module port <name> is not found in the port list

CAUSE: In a Verilog Design File (.v) at the specified location, you referenced the specified port name for the top-level module, but the specified port name is not found in the list of ports in the top-level module's Module Declaration.
ACTION: Edit the design to make sure the port name appears in the list of ports in top-level module's Module Declaration.

See also:

Section 12.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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