| CAUSE: | In a Verilog Design File (.v) at the specified location, you used a Parallel Block, which is a block surrounded by Fork and Join Statements. Although Verilog HDL supports Parallel Blocks, the Quartus II software does not support Parallel Blocks, and ignores all statements between the Fork and Join Statements. |
| ACTION: | Edit the design to remove the Parallel Blocks. You can replace Parallel Blocks with one or more Sequential Blocks, possibly inside separate Always Constructs. |
See also:
Section 9.8.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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