Quartus

Verilog HDL unsupported feature error at file <name> (line <number>): cannot synthesize MOS switch gate primitive

CAUSE: In a Verilog Design File (.v) at the specified location, you instantiated a nmos, pmos, or cmos MOS switch gate primitive. However, the Quartus II software does not support synthesis of MOS switch gate primitives.
ACTION: Edit the design to remove all MOS switch gate primitives. You can replace them with behavioral models of the basic gates, or you can rewrite the design in a behavioral style.

See also:

Sections 7.1, 7.5, and 7.7 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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