Quartus

Verilog HDL unsupported feature error at file <name> line (<number>): can't synthesize pullup or pulldown primitive

CAUSE: In a Verilog Design File (.v) at the specified location, you used a pullup or pulldown primitive. However, the pullup and pulldown gates are not supported for Integrated Synthesis, because resisitve pullup and pulldown primitives cannot be implemented in Altera devices, except as part of a tri-state driver driving a bidirectional pin.
ACTION: If you need to implement a tri-state driver driving a bidirectional pin, use a construct like the one shown in the following example:
if (enable == 1'b1)
begin   tri_out <= my_sig;
else
   tri_out <= 1'bz;
end
For all other cases, edit the design to use only logic value 1 and logic value 0.

See also:

Section 7.1 and 7.8 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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