CAUSE: | In a Verilog Design File (.v) at the specified location, you declared a real variable data type. Although Verilog HDL supports real variable data types, this type is not supported in the Quartus II software. |
ACTION: | Change the data type of the variable to something other than real . |
See also:
Section 3.9 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
- PLDWorld - |
|
Created by chm2web html help conversion utility. |