| CAUSE: | In a Verilog Design File (.v) at the specified location, you used an Event Trigger Statement. Although Verilog HDL supports Event Trigger Statements, they are not supported by Integrated Synthesis. |
| ACTION: | Remove the Event Trigger Statement from the design. If the Event Trigger Statement is being used to trigger an Always Construct in another module, you can combine the two modules to eliminate the need for an Event Trigger Statement. |
See also:
Section 9.7 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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