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VHDL Case Statement error at <location>: Case Statement expression has <type> type, but must have discrete type or one-dimensional array type with character type elements

CAUSE: In a Case Statement at the specified location in a VHDL Design File (.vhd), you specified a Case Statement expression with the specified type. However, the expression must have a discrete type or a one-dimensional array type that has an element base type that is a character type. This error may occur when using a Case Statement to implement RAM in a design.
ACTION: Change the Case Statement using temporary variables and nested Case Statements.

See also:

Section 8.8 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual

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