Quartus

VHDL error at <location>: allocators are not synthesizable


CAUSE: In a VHDL Design File (.vhd) at the specified location, you used an allocator to create an object by allocating free memory. However, allocators are not synthesizable.
ACTION: Make sure you do not use any allocators in the design, that is, you do not try to create any objects by allocating free memory.

See also:

Section 7.3.6 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual

- PLDWorld -

 

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