| CAUSE: | In a VHDL Design File (.vhd) at the specified location, the named formal parameter is already associated with an actual parameter. A likely reason for this is that the formal is a constant generic or inputparameter to which you are now assigning a full value. |
| ACTION: | Check your parameter lists for the above possibilities, and correct the statement. |
See also:
The IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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- PLDWorld - |
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