| CAUSE: | In a VHDL Design File (.vhd) at the specified location, you used a formal parameter in an expression. However, the formal parameter is illegal for this expression. A common cause of this error is when a discrete range is being inferred from the type of the formal parameter. Refer to Section 6 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual for more information on the restrictions for formal parameters. |
| ACTION: | Remove the formal parameter, or make sure the formal parameter is legal. |
See also:
Sections 2.1 and 7 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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