In an Association List at the specified location in a VHDL Design File (.vhd), you used named association to map an actual parameter to the specified formal parameter of an item (such as a component or function). However, you did not declare the formal parameter for the item. For example, the Association List in the following code assigns the actual parameter i to the formal parameter i of the component dff, but the Component Declaration for dff does not declare a formal parameter i:

ENTITY err IS
   PORT
   (
      clk   : IN   BIT;
      i     : IN   BIT;
      o     : OUT  BIT
    );
END err;
	
ARCHITECTURE a OF err IS
   COMPONENT dff
      PORT (d, clk : IN  BIT;
            q      : OUT BIT);
   END COMPONENT;
BEGIN
   dff1 : dff PORT MAP (i=>i, q=>o, clk=>clk);
END a;

You must declare a formal parameter before you assign an actual parameter to it.