| CAUSE: | In a VHDL Design File (.vhd) at the specified location, you used a formal parameter. However, the formal parameter is illegal, for example, the implied type of the formal parameter may not be the same as the type of the return value in a Subprogram Declaration. Refer to Section 6 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual for more information on the restrictions for formal parameters. |
| ACTION: | Remove the formal parameter, or make sure the formal parameter is legal. |
See also:
Section 2.1 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |