In a VHDL Design File (.vhd) at the specified location, a constraint cannot be applied to the range because they are not compatible. For example, in the following code, BIT_VECTOR is defined over NATURAL, so a subtype cannot be defined over INTEGER:

type BIT_VECTOR is ARRAY (NATURAL RANGE <>) of BIT;
subtype MY_BIT_VECTOR is BIT_VECTOR (INTEGER RANGE <>);