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VHDL Case Statement error at <location>: Case Statement choices must cover all possible values of expression

CAUSE: In a Case Statement at the specified location in a VHDL Design File (.vhd), you specified choices for a Case Statement expression. However, the choices do not cover all possible values of the expression. The choices must cover all possible expression values.
ACTION: Add choices for all possible values of the expression, or add an OTHERS choice, which covers all possible values that are not included in the other Case Statement choices.

See also:

Section 8.8 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual

- PLDWorld -

 
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