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VHDL Variable Assignment Statement error at <location>: target object <name> must be variable or aggregate

CAUSE: In a Variable Assignment Statement at the specified location in a VHDL Design File (.vhd), you used the specified target object, which is not a variable or an aggregate. However, the target object of a Variable Assignment Statement must be either a variable or an aggregate.
ACTION: Change the target object into a variable or an aggregate, or change the Variable Assignment Statement into an appropriate construct (for example, if the target object is a signal, change the Variable Assignment Statement into a Signal Assignment Statement).

See also:

Section 8.5 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual

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