| CAUSE: | In a Subtype Declaration at the specified location in a VHDL Design File (.vhd), you declared a subtype for the specified type. However, you specified a range for the subtype that exceeds the bounds of the range that you specified for the type in a Type Declaration. The range for the subtype must be a subset of the range for the type on which the subtype is based. |
| ACTION: | Change the range for the subtype or the type so that the range for the subtype is a subset of the range for the type. |
See also:
Sections 4.1 and 4.2 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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