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VHDL Interface Declaration error in <location>: interface object <name> of mode out cannot be read. Change object mode to buffer or inout.

CAUSE: In an Interface Declaration at the specified location in a VHDL Design File (.vhd), you declared the specified interface object with a mode of OUT. Integrated Synthesis attempted to read the value of the interface object, but cannot do so because the interface object has the mode OUT.
ACTION:

Change the mode of the interface object to inout or buffer, or use a temporary internal object for the interface object. The following example shows how you can use a temporary internal object:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY example IS
   PORT
   (
      ena   : IN   BIT;
      i     : IN   BIT;
      o     : OUT  BIT
   );
END example;
 
ARCHITECTURE a OF example IS
   SIGNAL tmp : BIT;
BEGIN
   PROCESS (ena, i)
   BEGIN
   CASE ena IS
      WHEN '1' =>
         tmp  <= i;
      WHEN OTHERS =>
         tmp  <= tmp;
   END CASE;
   END PROCESS;
   o <= tmp;
END a;

See also:

Section 4.3.2 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual

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