| CAUSE: | In a Port Map Aspect at the specified location in a VHDL Design File (.vhd), you used a positional Association List to associate actual ports with the formal ports of a block or component. However, the positional Association List contains more actual ports than there are formal ports in the block or component. The number of actual ports in the positional Association List must be the same as the number of formal ports in the block or component. |
| ACTION: | Remove the extra actual ports from the positional Association List. Make sure that the actual ports are ordered so each corresponds to the correct formal port. To avoid receiving this message in the future, replace the positional Association List with a named Association List. |
See also:
Section 4.3.2.2 and 5.2.1.2 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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