| CAUSE: | In a Signal Declaration at the specified location in a VHDL Design File (.vhd), you declared a signal. However, you used the undefined range symbol (<>) for the signal. A signal must have a defined range. |
| ACTION: | Define a range for the signal. |
See also:
Sections 3.2.1 and 4.3.1.2 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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