Quartus

VHDL expression error at <location>: operands for operator <text> must have equal length

CAUSE: In a VHDL Design File (.vhd) at the specified location, you specified an expression. However, the operands for the specified operator in the expression have different lengths. The operands must have equal lengths.
ACTION: Make sure all the operands for the operator have the same length.

See also:

Section 7 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual

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