Quartus

VHDL syntax error: experienced unexpected end-of-file -- delimiter or keyword may be missing

CAUSE: In a VHDL Design File (.vhd), Integrated Synthesis experienced an unexpected end-of-file.
ACTION: Make sure you did not omit semicolons, keywords, or other necessary delimiters or text from the VHDL Design File.

See also:

The IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual

- PLDWorld -

 
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