| CAUSE: | In a VHDL Design File (.vhd) at the specified location, you used an unconstrained variable. However, in the context in which the variable is being used, the variable must be constrained. |
| ACTION: | Changed the unconstrained variable to a constrained variable. |
See also:
Sections 4.3.1.3, 4.3.2.2, and 8.5 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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