| CAUSE: | In a Loop Statement at the specified location in a VHDL Design File (.vhd), you used a WHILE iteration scheme condition that contains one or more signals. However, the condition must be an expression of integer variables that contains no signals. |
| ACTION: | Remove any signals from the WHILE iteration scheme condition. |
See also:
Section 8.9 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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