Quartus

VHDL Signal Assignment Statement error at <location>: Signal Assignment Statement must use <= to assign value to signal <name>

CAUSE: In a Signal Assignment Statement at the specified location in a VHDL Design File (.vhd), you used something other than <= to assign a value to the specified signal. However, you must use <= to assign a value to a signal.
ACTION: Make sure you use <= in the Signal Assignment Statement.

See also:

Section 8.4 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual

- PLDWorld -

 
Created by chm2web html help conversion utility.