CAUSE: | In a Subprogram Declaration at the specified location in a VHDL Design File (.vhd), you used the specified mode for a formal parameter. However, the formal parameter must have a mode of IN , INOUT , or OUT . |
ACTION: | Change the mode of the formal parameter to IN , INOUT , or OUT . |
See also:
Section 2.1.1 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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