You performed one of the following actions on the specified design:

• Started a compilation
• Started a timing analysis
• Started an analysis and elaboration
• Ran a functional or timing simulation
• Started a SignalProbe compilation
• Started a netlist extraction and synthesis
• Analyzed a file
• Created an AHDL Include File (.inc)
• Created a Block Symbol File (.bsf)
• Created a VHDL Design File (.vhd) or Verilog Design File (.v) for the current BDF
• Started the Design Assistant
• Generated HardCopy files
• Started a software build

The message text indicates which action occurred.