Quartus

Clock signal <name> has estimated HardCopy fmax <number>

CAUSE: You ran a timing analysis on the current design and then performed a HardCopy performance estimation on the design. The Performance Estimator is indicating the estimated HardCopy fMAX for the specified clock signal in the design.
ACTION: No action is required.

See also:

Running a Timing Analysis

- PLDWorld -

 
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