| CAUSE: | The Timing Analyzer found a combinatorial loop of the specified number of nodes in the netlist. Combinatorial loops may be caused by design errors. For example, by the incorrect use of an If Statement (VHDL), If Then Statement (AHDL), or If-Else Statement (Verilog HDL) in a design file. Additional messages list the names of the nodes in the loop. |
| ACTION: | If the combinatorial loop is intentional, no action is required. If you want to eliminate the combinatorial loop, check your source files and make sure that all If Statements have a corresponding Else Statement. |
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