Quartus

<+/-> <Inverted or Non-Inverted> clock path from clock <name> to destination has <high or low> pulse width of <time>

CAUSE: The Timing Analyzer is reporting the specified actual pulse width along the specified inverted or non-inverted clock path due to either the clock low (tCL) or clock high (tCH) limits inherent in the current target device.
ACTION: No action is required.

See also:

Overview: Using the Timing Analyzer
Running a Timing Analysis

- PLDWorld -

 
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