Quartus

fmax restricted to Clock High delay (<time>) plus Clock Low delay (<time>) : restricted to <time>. Expand message to see actual delay path.

CAUSE: The Timing Analyzer is reporting that the fMAX of the design is restricted to the specified performance due to the specified Clock Low (tCL) and Clock High (tCH) I/O switching frequency limits inherent in the target device you selected for the current design. The submessages of this message list the individual delay path times.
ACTION: No action is required. If you want to increase the performance of the specified clock beyond the specified I/O switching frequency limit, specify a different device.

See also:

Running a Timing Analysis
Specifying the Device Family & Device for Compilation

- PLDWorld -

 
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