Quartus

LVDS receiver input skew margin for data pin <name>, LVDS receiver channel <name>, and clock <name> is <time>

CAUSE: The Timing Analyzer is reporting the specified LVDS receiver input skew margin (RSKM)` for the specified data pin, LVDS receiver channel, and clock in an LVDS circuit in the design.
ACTION: No action is required. You can view the results of this timing analysis in the RSKM section of the Compilation Report.

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