| CAUSE: | The Timing Analyzer is reporting that two registers in a delay path are controlled by clocks that differ by an inverter. When this condition occurs, the Timing Analyzer assumes, by default, that both clocks have a 50% duty cycle (that is, that the signal only has half the clock period to travel from one register to the other). Therefore, the Timing Analyzer arrives at the fMAX calculation by dividing the fMAX without the inversion by two. |
| ACTION: | If you want the Timing Analyzer to assume a 50% duty cycle for both clocks, no action is required. Otherwise, you must specify a particular duty cycle for the clocks by creating clock settings. |
See also:
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- PLDWorld - |
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