| CAUSE: | The Timing Analyzer has detected the specified node, which could be an undefined clock, but which drives only latches or write or read enable signals in an Embedded System Block (ESB). Therefore, the Timing Analyzer will use it as the clock for tSU and tH calculations, but will not use it to compute fMAX. |
| ACTION: | Altera recommends that you create clock settings and assign the clock settings to the pin(s) that are functioning as clocks in the design. If you do not want the Quartus II software to treat a pin feeding the clock input of a register as an undefined clock, you can turn on the Not a Clock assignment for the pin. |
See also:
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- PLDWorld - |
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