Quartus

Delay from clock to LVDS transmitter data output <name> is <time>


CAUSE: The Timing Analyzer is reporting the specified delay from the clock to the LVDS transmitter data output in an LVDS circuit in the design.
ACTION: No action is required. You can view the results of timing analysis in the Compilation Report.

- PLDWorld -

 

Created by chm2web html help conversion utility.