| CAUSE: | In an Assertion Statement at the specified location in a VHDL Design File (.vhd), you defined the specified assertion. However, the assertion is never true. |
| ACTION: | To avoid problems in the future processing of the design, or to avoid receiving this message in the future, change the Assertion Statement or its surrounding logic so the assertion is not always false. If you expect the Assertion Statement to always be false, no action is required. |
See also:
Section 8.2 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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