| CAUSE: | In a VHDL Design File (.vhd) at the specified location, you specified an object that is either a variable in a process or an item in an array. However, the design never uses the object on the right-hand side (RHS) of an expression. If the object is not used at a later stage in the design process (for example, when stitching different parts of the design together), and if the object is not eliminated during synthesis, the object becomes a floating net. |
| ACTION: | Make sure the object is used at a later stage in the design process, or is eliminated during synthesis. If necessary to prevent the object from becoming a floating net, remove the object. |
See also:
The IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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- PLDWorld - |
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