CAUSE: | You used the Create/Update > Create Design File from Selected Block command (File menu) to create the specified Verilog Design File (.v), VHDL Design File (.vhd), Text Design File (.tdf), or Block Design File (.bdf) from the selected block. The Quartus II software generated the design file without errors. |
ACTION: | Click OK to close the message dialog box. |
- PLDWorld - |
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