| CAUSE: | You used the Create/Update > Update Design File from Selected Block command (File menu) to update the specified Verilog Design File (.v), VHDL Design File (.vhd), or Text Design File (.tdf) for the selected block. However, the design file was not created by the Quartus II software, and the Quartus II software will place the code generated to update the file at the end of the Verilog Design File, VHDL Design File, or TDF. |
| ACTION: | No action is required. You may need to manually edit the design file to incorporate the additional code at the end of the file. |
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